1. Field of the Present Invention
The present invention generally relates to the field of electronic circuits and, more particularly, to a level shifter circuit suitable for use in a digital electronic device.
2. History of Related Art
Level shifter circuits are used in digital electronic devices to enable a translation within the device from one voltage level to another. Referring to FIG. 7, a digital electronic device is represented by reference numeral 10. Device 10 as depicted includes first circuitry 12, a level translation unit 14, and second circuitry 16. The operating supply voltage provided to first circuitry 12 differs from the supply voltage provided to second circuitry 16. In the depicted embodiment, for example, first circuitry 12 is provided with a supply voltage Vdd while second circuitry 16 is provided with a supply voltage HVdd. Circuits in first circuitry 12 typically comprise those circuits within device 10 capable of operating at a reduced voltage. All other factors remaining constant, operating at a reduced voltage beneficially reduces power consumption. Accordingly, it is desirable to reduce the supply voltage to as much circuitry as possible without jeopardizing the functionality of device 10. In any design, however, there will be circuits (second circuitry 16) that require the full supply voltage for which the technology was designed. These circuits may include circuits that comprise a critical speed path, circuits that are required to drive a significant current, and so forth.
To accomplish a reduced supply voltage for a portion of the device while providing the remainder of the device with a full supply voltage, a level shifter is typically necessary. Referring to FIG. 8, a circuit segment 20 is depicted in which a first inverter 22 comprising a p-channel transistor 26 and an n-channel transistor 24 is connected to a second inverter 28 having a p-channel transistor 32 and an n-channel transistor 30 connected as shown. The voltage supplied to first inverter 22 is Vdd while the voltage supplied to second inverter 28 is HVdd. When the input to first inverter 22 is LO, the output node 25 is at Vdd. In the absence of a level shifting circuit, this Vdd output voltage on node 25 may be connected to the input of an inverter circuit, such as inverter 28, that is supplied with the second supply voltage HVdd. If HVdd is greater than Vdd, there is a voltage difference (Vgsp) across the source and gate terminals of p-channel transistor 32. If Vgsp approaches the threshold voltage of p-channel transistor 32, the transistor may turn on thereby creating an undesired current path between HVdd and ground. If, for example, HVdd is 1.5 V and Vdd is 0.9 V, Vgsp is roughly −0.6 V. As a rule of thumb, the threshold voltage for MOS transistors is roughly ⅓ of the supply voltage. Thus, the Vt of transistor 32 is roughly −0.4 to −0.5 volts. It will be appreciated, therefore, that transistor 32 is undesirably biased to be turned on and that a current path between HVdd and OUT occurs.
Level shifter circuits are intended to address this potential problem. FIG. 1 illustrates a conventional level shifter circuit 100. The basic level shifter circuit 100 includes a first transistor pair 102 and 104 having source/drain node connected in series between HVdd and ground and a second transistor pair 106 and 108 with source/drain nodes connected in series between HVdd and ground. Transistors 102 and 104 share a common node (A) and transistors 106 and 108 share a common node (the output node). Node A is connected to the input or gate of transistor 106 while the output node is connected to the gate of transistor 102. Transistors 102 and 106 are p-channel devices while transistors 104 and 108 are n-channel. The gate of transistor 104 is connected to an input node while the gate of transistor 108 is connected to the output of an inverter 110. The input node is also connected to the input of inverter 110 whereby the gate of transistor 108 receives the logical complement of the signal on the input node. The input node receives a signal from a circuit or logic gate that uses Vdd as a supply voltage. Thus, the logic HI level of the input signal is equal to Vdd.
Operationally, level shifter 100 is relatively simple. When the input node is LO, transistor 108 turns on to pull the output node LO. As the output node goes LO, transistor 102 turns on thereby pulling node A to HVdd, which cuts-off transistor 106. When the input node is HI, transistor 104 turns on thereby pulling node A LO and turning on transistor 106 to pull the output node to HVdd. In this manner, the Vdd input signal is shifted to an HVdd signal suitable for use in a circuit supplied with an HVdd supply voltage.
Ideally, the transistors in level shifter 100 turn on and off instantaneously so that the transition time is zero and no current path ever exists between HVdd and ground. In reality however, transistors 102 through 108 have finite impedances, even when fully on, that affect circuit performance. When the input node transitions from HI to LO, for example, node A must charge from Vss to a critical voltage of roughly HVdd−Vtp (where Vtp is the absolute value of the Vt of transistor 106) to cut-off transistor 106. Because node A is connected to the inherently capacitive gate terminal of transistor 106, however, the node A voltage cannot transition instantaneously. Instead, the node A voltage rises smoothly as the node is charged to HVdd. Before node A reaches the critical voltage, transistor 106 is on. Meanwhile, the node B at the input of transistor 108 is driven rapidly by the input signal from LO to HI thereby turning on transistor 108. If node B transitions HI faster than node A, transistors 106 and 108 will be on simultaneously for some finite duration. During this time, current flows freely and undesirably from HVdd to ground trough the source/drain paths of transistors 106 and 108. This undesirable current is referred to herein as the switching current or short-circuit current.
A complementary situation occurs when the input goes from LO to HI wherein a short-circuit current flows through transistors 102 and 104 while the output node charges from LO to the critical voltage. Generally speaking, however, because transistors 106 and 108 are typically required to drive input signals, they are typically designed as larger devices that conduct more current than transistors 102 and 104. Thus, the short-circuit current is of greater concern for the HI to LO case than vice versa for a typically designed level shifter.
It would therefore be desirable to implement a level shifting circuit that incorporates a short-circuit current reduction mechanism in conjunction with a transition time booster mechanism to compensate for transition time degradation attributable to the short-circuit reduction mechanism.